A bit of confusing deadline.
As noted in the report, the future success of Samsung’s HBM4 will hinge on the development of sixth-generation (1c) DRAM—fabricated using a 10nm-class process—by its memory division. The 12-layer HBM4 product will integrate this 1c DRAM with the logic die.
They are still using a 10 nm fabrication node for DRAM.
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Can they get a benefit from going smaller with a single transistor/capacitor for each bit. Like what is the surface area and separation required to store enough electrons without coupling charge to adjacent bit cells?
