IIRC, SDR -> DDR4 were a single 64bit wide data bus to the DIMM, but with DDR5 that was changed to a 2x 32bit data bus, thus allowing 2x 32bit reads to the DIMM to done independently. Due to the change to 32bit wide channels we can now have non power of 2 sizing of the actual memory chip itself… (basically the addressing modes changed to allow this).
I found this comment:
And that seems to be backed up under “subchannels” on the ddr5 Wikipedia page.
Neato, thanks for teaching me something new