• HorreC@lemmy.world
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    26 days ago

    I dont know what they are aiming for on the lower core count one, maybe it super weird binning of really good cores just only 4 made it on each die and this is them being like ok we wanna save money on wasted silicon lets make a dual chiplet and make it an x3d now that we have the cache thing work over duals. I cant see the reason for what the leak suggests on that small one.

    • MHLoppy@fedia.io
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      26 days ago

      That’s an interesting take, but I reckon it’d be a tough sell given the latency penalty it’d bring with it to do that, especially if the core scheduling is ever “wrong” and ends up unnecessarily bouncing between the dies. Guess we’ll have to wait and see!

      • HorreC@lemmy.world
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        26 days ago

        Yeah it was the only reason I could think of on the fly that they are even doing this. Maybe with the I/O improvements that are in the threadripper maybe there is some locking down of how caching works with this so they tend to understand where the information is, and the cores it will put to use it. But I would think that would be more of a scheduler task, but I dont understand that level very well, or movements in that area.